(1) Field of the Invention
The invention relates to the field of semiconductor manufacturing, and more specifically to a method to completely and satisfactorily fill high aspect ratio gaps.
(2) Description of Prior Art
The conventional method of forming conducting lines and connecting vias within the construct of a semiconductor device is to deposit a layer of conducting material, such as aluminum, on the surface of a semiconductor using for instance a sputtering technique. Over this layer of conducting material is deposited a layer of photoresist, this photoresist is patterned and etched such that the conducting material that is to stay in place (to form the conducting lines or vias) is covered or protected by the photoresist. The unwanted conducting material is then removed, typically using anisotropic plasma etch. The openings created by the removal of the conducting material are filled with a dielectric material such as an oxide. The surface of the combined patterns of conductive material and dielectric can further be planarized by using a Chemical Mechanical Polishing (CMP) process that completes the creation of conducting lines or vias.
The formation of air gaps between conducting lines of high speed Integrated Circuits (IC's) is typically a combination of the deposition of a metal layer, selective etching of the metal layer to form the desired line patterns, the deposition of a porous dielectric layer or a disposable liquid layer which is then selectively removed to form the desired air-gaps.
By combining bias sputtering deposition techniques with plasma-enhanced deposition, a high deposition rate has been established for CVD oxide. The deposited CVD oxide is free from particles from chamber walls and from metallic contamination and can furthermore produce films of low stress. Needed to accomplish this deposition however is a source of high density, low-energy ions. High-density plasma sources provide the capability to combine CVD SiO2 and bias sputtering for high quality Intra-Layer Dielectric (ILD) at a low temperature.
Recent requirements for the creation of holes within deep layers of either conducting or other materials have resulted in creating openings that have aspect ratios in excess of 3. It is beyond the capability of the existing techniques to fill gaps of this aspect ratio with High Density Plasma-oxide (HDP-oxide). This lack of adequate filling of gaps also occurs for holes that have a reentrant spacer profile. A reentrant spacer profile is a profile where the walls of the openings are not vertical but are sloped, this sloping of the walls makes complete penetration of the HPD-oxide into the hole difficult and, under certain conditions, incomplete.
As a consequence of incomplete deposition of HDP-oxide into high aspect ratio holes, keyholes or deposition irregularities will be formed. These keyholes or deposition irregularities are characterized by non-homogeneous deposition that form in the deposited HDP-oxide.
FIG. 1 shows Prior Art deposition of HDP-oxide 12 over a pattern 14 of polysilicon. The pattern 14 can be deposited on the surface of a semiconductor substrate 10 or on any other surface within the formation of a semiconductor device. The resulting keyhole 16 appears within the hole 13 and is approximately centered within the hole. The keyhole is formed due to incomplete flow of the deposited HDP-oxide resulting in molecular tension and lack of uniform distribution of the deposited HDP-oxide.
FIG. 2 shows the same Prior Art phenomenon in the formation of the keyhole 16, in this example spacers 18 (for the SAC process) with a reentrant profile have been added to the polysilicon pattern 14. In the example shown in FIG. 2, the formation of the keyhole 16 can be more severe since the reason for the formation of the keyhole is further emphasized by the profile of the spacers 18. This profile shields portions of the holes between the poly pattern 14 from the source of the HDP-oxide deposition, this shielding further amplifies the formation of the keyhole 16.
The indicated condition for the formation of a keyhole can also occur where a high aspect ratio through-hole is formed by RIE and where the formation position of the through-hole may deviate from the correct position due to mask misalignment or a process variation. The created through-hole can in this case exhibit a profile that inhibits complete and uniform deposition of HDP-oxide.
The indicated existence of keyholes is, from a semiconductor manufacturing point of view, highly undesirable. Keyhole formation can be the cause of shorts between conducting layers, high leakage currents and unsatisfactory planarization characteristics. What is needed therefore is a method that eliminates the formation of keyholes. This method can solve the problem of keyhole formation by improving the filling of the holes or by reducing the aspect ratio of the hole or by improving the reentrant spacer profile. The present invention addresses the elimination of the keyhole by applying all three indicated problem solutions.
U.S. Pat. No. 5,814,564 (Yao) shows an etch back method to planarize an interlayer having a critical HDP-CVD deposition process.
U.S. Pat. No. 5,756,396 (Lee et al.) teaches full spacers on metal line sidewalls.
U.S. Pat. No. 5,262,352 (Woo) Method for forming an interconnection structure for conductive layers—shows a method for forming spacers on metal line sidewalls.
U.S. Pat. No. 5,462,893 (Matsuoka et al.) shows a spacer used as an etch stop on a metal line.